`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/01/01 20:09:25
// Design Name: 
// Module Name: CheckHit
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module CheckHit(
	input wire clk,
	input wire [9:0] x0,
	input wire [9:0] y0,
	input wire [9:0] x1,
	input wire [9:0] y1,
	output reg hit
    );
    parameter r = 3;
    wire [19:0] x_sqr;
    assign x_sqr = (x0-x1)*(x0-x1);
    wire [19:0] y_sqr;
    assign y_sqr = (y0-y1)*(y0-y1);
    always @ (posedge clk) begin
    	if (x_sqr+y_sqr<r*r) hit<=1;
    	else hit<=0;
    end
endmodule
